I m kind of working on a simple STSPin32F0A based design using 3x Dual-N Channel Mosfet.
Idea to drive a simple Bldc Motor.
However having questions regarding the Mosfet PCB routing.
Well, you’ve already said it: a single via won’t support very high currents. So the way I see it is:
For either solution I think you will need some more space on the board…
Are you planning to run SimpleFOC on it? Because this chip has only 32kB of flash, so it won’t be enough for SimpleFOC or Arduino framework… you’ll have to write your own firmware without Arduino, or maybe use ST-Micro’s motor control SDK.
One way or another, the board is going to get bigger to make room for vias. The general rule is 2 amps per via.
Either increase the length so you can fit a bunch of vias between the mosfets, or rotate the mosfets 90 degrees and increase the width so you can fit vias to the left of them.
If you’re willing to do some manual work, the most compact solution I can think of is to put one large hole (maybe 1mm) next to each pin, and solder copper wires through them. But even that would need more space between mosfets than you currently have.
My previous attempt to build a 4 in1 ESC failed.
humbled by that experience, moved to single IC that has integrated MCU+ H-bridge.
My goal is to run motors [1700-2400kv] reasonable rpm [upto 5k].
Should be able to handle current upto 20A.
made modifications [ added vias at Vshunt]
I will be using ST’s frame work or using sts_esc_firmware
I have added 8 vias.
5 vias are 0.9/0.6mm
3 vias are 0.6/0.3mm
Unfortunately the majority of those won’t help. SE3082G only has one ground pin, the one between the two gate pins with the 3 vias. The left pin is not connected to anything internally.
Oh!, I see…
Thanks for you input, Have you used SE3082G in your Project, How is the mosfet performance they claim 80A!!
STSPIN32F0A internal Half-bridge provides 12V Vgs.
Scratch my reply… saw your bunch of Projects with SE3082G… 
Yes, I’m quite fond of them for their low cost and nice form factor where you can practically eliminate the PCB copper from being the conductivity bottleneck. But that single ground pin is a bottleneck nomatter what you do. I wish they hadn’t wasted a pin.
80A is definitely more than you can realistically expect. 10A runs cool, 15A gets a little warm without a heatsink. 40A will start glowing and melt after a few seconds without a heatsink, but is probably doable with heatsink and fan.
I used the SE3082G in the Lepton design.
You need 4OZ copper. Vias won’t help.
I never understood the fascination with that particular silicon. Underpowered, overpriced, and locked into a pin-out. The only marginal edge is the integrated buck and ldo. And then, yet, the LDO is 12V and the buck is 3.3V. The G071 and DRV8300 combo is cheaper, more powerful and completely customizable.
Cheers,
Valentine
I started with 4 in 1 design using F051 + FD266Q without understanding much of what is what.
did mistakes like not having the decoupling capacitors for mcus, Boot pin floating.
OP-AMP was given VBatt feeds.
Mosfets didn’t had proper pads.
Though i used 20z outer and 1oz inner. The board failed to boot even swd pins didn’t respond.
made another attempt with single ESC[f051 + FD266Q] the Voltage regulator had wrong footprint blew the board as soon i powered it up.
that’s how I landed up on this
So now i landed up at stspin32F0.
Even here I m facing the challenge how to route the V_Shunt, my all mosfet Gnd is connected to shunt resistor 1mohm.
There are many board designs here, it may be usefultto see what others have done to help.
valentine
sure, can you pls share good good working designs.
Thanks
Abhinav
Better!
I’d recommend 0.3mm vias under the pads unless you’re paying big bucks for plugged and capped. In addition to directly reducing the solder joint area by having open holes under the pads, they also suck solder from the remaining joint, so you don’t want too much potential volume lost.
Where is the 5mm wide +VM fill? If it’s under the mosfets, then it’s being almost entirely cut by the vias on the out pads. I’d recommend removing at least half the vias in that case.
