FOC Algorithm Flow Chart

I have created the flow chart for FOC, could you please review and let me know it is correct or modifications to be done. Please help.

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What exactly are your trying to convey to the reader?
I can see the PWM timer counting up and down and a timeline on which some events with corresponding actions are mentioned. These all seem to be correct with respect to what happens in simplefoc (based on my limited understanding of the library) but aren’t true in all FOC implementations. you can make FOC work without center aligned PWM for example. Also while as I said I don’t see any errors exactly I also don’t know if you should modify it as I don’t know what the purpose of the chart is. That’s why I started with asking what you are trying to convey. Maybe it would be helpful to add the counter values for the current duty cycle on the rising and falling line? Maybe it would be helpful to extend the diagram a couple of cycles and show what changes are made by the algorithm? I don’t know the answer as I don’t know what you are trying to show/teach the reader.

In some scenarios, where the MCU does not have the timer/frequency for dual_slope up/down counting it may be preferred to just count up. This will drastically increase the resolution, in some random scenarios.

What are the benefits of dual_slope. Higher precision?

Nice work!! I like your chart. I think it is correct, but for the case of low-side current sensing. When using inline current sensing, there is no ADC trigger that needs to be synchronised to the PWM, and the ADC read and FOC algorithm can execute at any time, asynchronously to the PWM.

If you wanted to, you could add to your diagram the timer compare level (a horizontal line) and the PWM waveform that it generates - this is what determines the duty cycle.

Will your diagram be open source (Creative Commons)?

The benefits are twofold:

  1. PWM signals of the three phases are aligned with a common on-time in the middle. This is needed for most low-side sensing schemes, as the ADCs will sample their channels at the same time.

  2. I believe centre aligned signals exhibit nicer behaviour because they are all “in-phase”. Simple PWM will have the effect of “jumping around” the peak-to-peak distance as the duty cycle varies. So there is a duty-cycle (amplitude)-dependent phase-shift introduced. I don’t have the math on hand to really describe it well, and may be wrong, perhaps someone else here knows more about it…

Thank you. Yes it can be open source, but i don’t know how to make it etc. I will update the diagram and also details i will add as per the review comments from other members.

This is interesting.

With regards to current sensing, are there better (and worse) positions within the timing diagram to perform the ADC to avoid switching induced noise? Is it a problem at all?

Also, would there be any merit in performing the currents ADC and the subsequent foc calcs as close as possible to the duty cycle update time (right side of the chart) to best capture the effect of the foc calculations of the previous cycle?

I realise this might make it more difficult to cater for variable PWM frequency.


Hi @rmeldo,

Near the middle of the on-time for the low side FET is probably as good as it will get in terms of the switching noise. At low duty cycles this on-time isn’t very long, so if you push it too much further then the ADC may not have enough time. Also, the PWM hardware of most MCUs provides a convenient interrupt/event at the middle of the on-time (since it corresponds to the count limit set for the timer).

Good question! While the diagram shows the FOC calculations as fitting within one PWM cycle, this will actually only be the case for very fast MCUs.
And while the ADC (in low side sensing) is synced to the PWM, the FOC calculations are not, they run asynchronously in the SimpleFOC implementation.
So in real life, most BLDCs are run at >20kHz PWM frequency, to prevent audible commutation noise, but most MCUs run SimpleFOC’s main loop at a frequency of less than 20kHz.
So while you get 1 ADC sample per PWM cycle, you don’t necessarily use it. Depending on the iteration speed of the MCU you may only use every 5th sample or even less.

While increasing the loop speed is desirable, the commutation frequency is expected to be considerably lower than the PWM frequency… so the fact you’re not sampling/controlling at the PWM rate isn’t necessarily a problem.

Thank you
It makes sense.

Sure, but this leaves room for oversampling to for example 14bit if the native ADC is 12bit.

I have updated the diagram

with CCR (capture compare registers).

Hi, now you don’t sample in the middle anymore…
But what is the context for this diagram ? Is it the way it is implemented in SimpleFOC ?
There are different ways this could implemented.

For example in Motor workbench (page 53) of STM, they use CCR4 to be able to move the sampling point, accounting for the mosfet turn-on time, rise time and noise.

Ok, the context of the diagram is that i want to know my understanding is correct about the FOC, the phase current reading etc. I don’t have SimpleFOC board, i am using the STM32 board. I have some other doubts i raise it as separate thread.