Alright. Second PCB design but this time a bit more challenging than a linear hall. Its a DRV8323S breakout board with low-side sensing.
Its a 40mm x 40mm board. Those are 2.54mm Headers and should slot across the center of a breadboard.
Tell me how I did, or roast me. What ever suits you.
I plan to clean it up a bit more then release it on my Github. I’ll probably get around to that tomorrow.
I am planing on using some 30v, 60a (Package limited) mosfets. The board itself will be a four layer (I’m bad at cable management). I’ll probably use the defaults of 1oz outer and 0.5oz inner. This will mean that that I probably can’t safely push to the full 60 amps. That wont stop me though as I am no stranger to fireballs.
Limits are best found experimentally.
Something I only recently noticed is that the DRV8323S actually supports using the mosfet as a current shunt. That should be possible on my design if you short the shunts and cut the jumper. Then its a firmware change and it should run.
Yet another, but last thing, I’ve tied the grounds of the low voltage input and the high voltage input. Any good way to prevent death of components if the grounds do not have the same zero points?
IMHO It makes things much harder doing everything at the same time. I think it might be easier to create a working design without imposing extreme space constraints at the same time.
Then once it is working and debugged, see about making it smaller.
But also, designing for 60A current isn’t the easiest. In order to make it both handle 60A and be tiny in size will require a very good layout for inverter and power path, and considering the heat management right from the start.
A good source of inspiration could be race drone ESCs. For the small sized drones these are often even smaller than 50x50mm, but can handle huge currents. Keep in mind that in a drone they always have forced air cooling, so in other applications they would need a fan to keep cool.
An example of what I mean:
I suggest around 1000uF of capacitance, and try to pick capacitors with low ESR. Of course this depends on how much current you are trying to use and the switching frequency. More current generally means more capacitance, and higher switching frequency means less capacitance.
Overall it’s looking pretty good. A few more suggestions, you don’t have to follow all of these but they should increase performance slightly.
The circled areas seems to have vias doing nothing (except maybe heat dissipation?), I suggest you remove it and the area below, and shrink everything else down as well.
Try to make the gate traces as short as possible, for better MOSFET switching performance. If you shrink it down, have the MOSFETs closer to the driver, and put the driver in a more central location on the board it will help with this.
You can also have a look at my design which uses the same chip as a reference.
If you really want to have 60 amps, you will need to add some really good heatsinks maybe even a fan, and also lower RDSon MOSFETs, and you’ll also need heavy copper PCBs (at least 2oz on all layers). Please note that the number in the datasheet is mostly meaningless, because MOSFETs are almost always thermally limited. A more realistic estimate provided by the manufacturer is 21A continuous.
The target for the switching frequency depends on your motor inductance, generally with higher inductance motors you should use a lower switching frequency for lower power losses, and for lower inductance motors you need a higher switching frequency to reduce current ripple. I would say a typical range is 20-50KHz.
2.
For your digital signals on L2 you will not have any direct reference to GND since the layers above and below are Vin, and they will most likely have GND as a reference on the MCU board. Might work anyway, but not good practice and higher risk of problems.
3.
In practice you only have two layers for power since L2 and L3 are cut by signals, so Vin in on the top and GND on the bottom. So for 60A you will need something like a 80mm trace in theory, but you have more like 5mm.
4.
As mentioned, capacitors for the DC bus is important. Otherwise you will see a lot of reactive power there and your current will be even higher and with an ac component.
Does that mean that with perfect heatsinks, I would get 2 degrees C for every watt I put through them?
Kind of, but I would see it as pretty theoretically, it would be if the FET is directly connected to the heatsink. But a good heatsink would make a large difference.
My current stackup for filling the empty space is:
Vcc
GND
Vcc
Gnd
I would change to 6 layers, should not make a big difference in money. Then I would do something like
Top: Vin polygons to FETs / Signals to connector (no GND fill)
L2: GND fill
L3: Signals to MOSFETS (Could fill w GND)
L4: Vin plane
L5: GND plane
Bottom: Vin polygon or plane
So I can’t seem to find a good way to calculate an appropriate capacitance without just using a spice simulator (those seem hard ). Treating it like a buck regulator gives me an input capacitance of 15,000uF.
The thing is that you don’t really know how much you need until you have run the system. The ripple on the DC bus that’s what you wanna get rid of depends on switching frequency and how your driver and motor works together. You could start with 15k and then measure the ripple and adjust on the next iteration maybe?
No ground plane on the top or bottom?
Those can handle much more current than the inner planes so it seems odd to only do vin on the top and bottom.
This is basically what you have today, your top layer only have VIN and your bottom only have GND. My point was mainly that you don’t need to fill the rest of the board on those layers except for the paths to the FETs, since that’s were the currents will go. Then you might as well spare the Driver IC at least a little bit of the high current switching noise.
That’s fairly unfortunate. I actually did find a TI article on estimation of bulk capacitance. It gave a guideline then basically said to check with the simulations.
Yeah that will give you an as good start as possible.
Guessing it will be tight to fit the needed capacitance in? Is the size you have now of the board important for you?
Yep. Doesn’t fit on the board at all. I have two holes at the very edge and plan to hang the cap off the side.
One 1000uf cap is 12.5mm diameter if I remember correctly. The board is 40mm x 40mm total.
Yes an no. A project I have planned for the future needs a miniscule board. This is a pilot for that and will tell me if it’s even possible. I’ll proably need all the noise reduction tricks I can find too.
Aside from future plans, the only real limit I think I should keep it under is 50mmx50mm since JLC only charges $2 for 5. Makes it slightly easier if someone else wants to make a board for themselves.
Anyway, thank you for the detailed feed back. I’ll try to implement as much as I can for the next iteration.
Here’s JLC’s capabilities page PCB Manufacturing & Assembly Capabilities - JLCPCB
They can do 0.15mm holes if you’re willing to pay a lot. I used 0.25mm on my rework of Lepton and didn’t get charged extra, but then on Gooser it looked like anything under 0.3mm was going to cost me, so that’s what I used (with 0.45mm annular ring). 0.15mm for signal traces, 0.25mm for medium current like mosfet gates, and 0.45mm traces for higher current like power to the gate driver chip. 0.05mm grid snap, and 0.2mm clearance (I actually set it to 0.199mm because EasyEDA sometimes inappropriately reports collisions due to numeric accuracy tipping it over the threshold).
There are just heat dispation. I plan to mount a heating to the back so they would get some benefit from it.
If I iterate again, I’ll remove them.
I’ll keep that in mind for a redesign later. Hopefully it will be fine for this first batch…
I wish I would have found this before I started. This would have save a significant amount of time. I’ll definitely be taking a look at it later today.
I plan for there to be more aluminum than board.I doubt I’ll make it to the full 60 but I do want to see how close I can get.
I’ll probably also test a board with no heat sinking to see how it does which will probably get like 10amps because the low side MOSFETs have very little surface to disapate heat.
Each MOSFET will also disapate 12ish watts at 60 amps of draw. That could be a problem.
No ground plane on the top or bottom?
Those can handle much more current than the inner planes so it seems odd to only do vin on the top and bottom.
That’s fairly unfortunate. I actually did find a TI article on estimation of bulk capacitance. It gave a guideline then basically said to check with the simulations.
Funnily enough, I designed the majority of the minature board first. Micro controller and everything.
Then I realized the buck converter in the DRV8323RS cannot give 3.3v at 30v input.
I figured to keep things simple this time I’d split off the two first.
My final project doesn’t need the full 60A but it would allow me to derate for longer life.
And if something explodes, that creates a very visible indicator for the weak link on the board.
I have a super tiny 30amp ESC that I forgot on my desk. It was partly the inspiration for this.
It does depend where you put the ESC. I’ve seen some people shove them in the carbon fiber tube or in the body of a foam plane.
Forced air flow does not hurt though.
Apparently my JLC order was on hold. if you can modify the hole size/diameter as 0.2/0.45mm
I assume they mean the vias so I am asking for clarification.
I guess its board redesign time while I wait for a response.
Once I am done, I’ll start a new topic but with the correct format.
