# \#rpm

**URL:** https://community.simplefoc.com/tag/rpm/205.md

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## [Problems in Increasing Speed in FPGA based FOC Implementation](https://community.simplefoc.com/t/problems-in-increasing-speed-in-fpga-based-foc-implementation/7345)

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**Author:** [@mkfoccommunity](https://community.simplefoc.com/u/mkfoccommunity)\
**Replies:** 0\
**Last updated:** [June 23, 2025, 10:04am UTC](https://community.simplefoc.com/t/problems-in-increasing-speed-in-fpga-based-foc-implementation/7345 "2025-06-23T10:04:55Z")

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Hi all, I am currently working on implementation of FOC On FPGA. I am developing it by writing bare VHDL code, not using Matlab-Simulink or other block diagram based software. Referring this link for my 3phase BLDC PMS…